Some notes about powering off the CI20.

From the manual:

"25.4.2 HIBERNATE Mode

The purpose of hibernate mode is to save the power. When in hibernate mode, CORE will no power consumption.

If you want to use hibernate mode, please first make sure RTCCR.SELEXC is 0. When Software writes 1 to PD bit of HCR, the system at once enters HIBERNATE mode. The powers of CORE and IO are disconnected by PWRON pin, no power consumption to core and IO. When a wakeup event occurs, the core enters through a hibernate reset. Only CPM wake up logic and RTC is operating in HIBERNATE mode."

In arch/mips/jz4740/reset.c in the CI20-specific Linux 3.18 kernel and in the RTC driver in more recent mainline kernels (drivers/rtc/rtc-jz4740.c), the following things are done when powering off:

  1. The wakeup filter counter register (HWFCR) is initialised, presumably to set the minimum length of any pulse that will terminate hibernation.
  2. The reset counter register (HRCR) is initialised, presumably indicating the length of the hibernate reset pulse.
  3. The hibernate control register (HCR) is set to 1, causing the power-down (PD) bit to be set, indicating that hibernation, causing power-down, is to occur.

It seems that the hibernation mechanism may be responsible to manipulating the power on signal (PWRON), which is fed into the ACT8600 regulator's power enable (PWREN) pin, manipulating the power supply. Thus, the power on control register (PWRONCR) may not need to be manipulated directly.

Register Access

The RTC control register (RTCCR) must be tested with the write-ready field (WRDY, bit 7) set before accessing (reading or writing) the write-enable register (WENR). This register must be set with a particular pattern (0x0000A55A) and the write-enable field (WEN, but 31) tested as being set before proceeding to access other registers.

In other words, the procedure appears to be as follows (employed in drivers/rtc/rtc-jz4740.c in the Linux kernel):

  1. Wait for write-ready condition.
  2. Write the pattern to the write-enable register.
  3. Wait for the write-enable condition.
  4. Wait for the write-ready condition.
  5. Access the register to be updated.