LCD controller configuration.
Since the programming manuals tend to describe the LCD controller, this mostly reflects the information included therein.
| Register | Offset | Description |
| LCD_CFG | 0x000 | Display panel/transfer configuration |
| LCD_VSYNC | 0x004 | Vertical sync configuration |
| LCD_HSYNC | 0x008 | Horizontal sync configuration |
| LCD_VAT | 0x00c | Display vertical area |
| LCD_DAH | 0x010 | Display horizontal limits |
| LCD_DAV | 0x014 | Display vertical limits |
| LCD_PS | 0x018 | Lcd_ps |
| LCD_CLS | 0x01c | Lcd_cls |
| LCD_SPL | 0x020 | Lcd_spl |
| LCD_REV | 0x024 | Lcd_rev |
| LCD_CTRL | 0x030 | LCD peripheral control |
| LCD_STATE | 0x034 | Status |
| LCD_IID | 0x038 | Lcd_irq_id |
| LCD_DA0 | 0x040 | Desc_address_0 |
| LCD_SA0 | 0x044 | Source_address_0 |
| LCD_FID0 | 0x048 | Frame_id_0 |
| LCD_CMD0 | 0x04c | Command_0 |
| LCD_DA1 | 0x050 | Desc_address_1 |
| LCD_SA1 | 0x054 | Source_address_1 |
| LCD_FID1 | 0x058 | Frame_id_1 |
| LCD_CMD1 | 0x05c | Command_1 |
The 3.18 driver file drivers/gpu/drm/jz4780/jz4780_crtc.c features the following configuration register settings:
8-word descriptors (NEWDES)
Underrun recovery (RECOVER)
24-bit output (MODE_TFT_24BIT)
PS disable (PSM)
CLS disable (CLSM)
SPL disable (SPLM)
REV disable (REVM)
Pixel clock negative/falling edge polarity (PCP)
This seems to imply that the data enable, horizontal and vertical sync polarity are positive. The panel mode is unset, implying a generic TFT panel mode.
The driver appears to enable output FIFO overrun interrupts (OFUM) in the control register, resetting the controller if they occur during operation. Other drivers tend to enable overrun protection (OFUP) instead.
The driver enabled end-of-frame interrupts, sending vertical blanking events to the DRM infrastructure. End-of-frame conditions are activated by the DMA controller after frames have been transferred, and this is configured in the DMA descriptors.
The driver employs two 8-word DMA descriptors with the following format:
| Field | Description |
| Next | Physical address of next frame descriptor |
| Source | Physical address of source data to transfer |
| Frame | Frame identifier (for debugging) |
| Command | DMA command and transfer length (in words) |
| Offset | OFFSIZE: Offset in words between lines |
| Page width | PW: Number of words per line (16x16 block mode) |
| Command (smart LCD) | CNUM: Command number (smart LCD mode) |
| Position (LCD) | CPOS: Foreground position and properties |
| Foreground size | DESSIZE: Foreground size and alpha properties |
Note that the seventh word has two different interpretations depending on the CMD field (bit 29) of a transfer command.
In the driver, the next, source and frame fields are mostly comparable to those set by other drivers. However, the command is also initialised with a frame-enable flag.
The additional fields are initialised as follows:
Offset is set to zero
Page width is set to zero
Position is set to 0x2d000000 and 0x2f000000 for the respective descriptors (this sets the bits per pixel of OSD channel 1 to 18/24, non-premultiplied data, and two different alpha-related coefficients for the foreground data)
Foreground size has alpha set to 0xff and the size information of the frame set to height - 1 and width - 1 (apparently in pixels, not words)
Quite why these extra details need to be set up is not clear, but perhaps the OSD functionality must be enabled for the HDMI pipeline to work. Despite this, the OSD configure (OSDC) register is not apparently configured in the driver or elsewhere.
The 3.0.8 framebuffer driver (drivers/video/jz4780-fb/jz4780_fb.c) does configure the OSDC register with the following settings:
OSD is enabled (OSDEN)
Alpha blending is enabled (ALPHAEN)
Bit 16 is set with the cryptic comment "once transfer two pixels"
This driver only appears to configure the OSD control (OSDCTRL) register to enable the IPU clock on request.
Other interesting aspects of the 3.18 driver are the use of the RGB control (RGBC) and priority level threshold configure (PCFG) registers. The former is set up as follows:
RGB format enable is set (RGBFMT)
RGB odd line output is selected (OddRGB)
RGB even line output is selected (EvenRGB)
The priority level threshold configuration register is set up as follows:
LCD priority mode is set to "arbiter priority level" (Lcd_pri_md)
64-word highest priority burst length is set (HP_BST)
Three thresholds are specified: 511, 400, 256