LCD Controller

LCD controller configuration.


Since the programming manuals tend to describe the LCD controller, this mostly reflects the information included therein.

Register Offset Description
LCD_CFG 0x000 Display panel/transfer configuration
LCD_VSYNC 0x004 Vertical sync configuration
LCD_HSYNC 0x008 Horizontal sync configuration
LCD_VAT 0x00c Display vertical area
LCD_DAH 0x010 Display horizontal limits
LCD_DAV 0x014 Display vertical limits
LCD_PS 0x018 Lcd_ps
LCD_CLS 0x01c Lcd_cls
LCD_SPL 0x020 Lcd_spl
LCD_REV 0x024 Lcd_rev
LCD_CTRL 0x030 LCD peripheral control
LCD_STATE 0x034 Status
LCD_IID 0x038 Lcd_irq_id
LCD_DA0 0x040 Desc_address_0
LCD_SA0 0x044 Source_address_0
LCD_FID0 0x048 Frame_id_0
LCD_CMD0 0x04c Command_0
LCD_DA1 0x050 Desc_address_1
LCD_SA1 0x054 Source_address_1
LCD_FID1 0x058 Frame_id_1
LCD_CMD1 0x05c Command_1

JZ4780 HDMI Driver Specifics

The 3.18 driver file drivers/gpu/drm/jz4780/jz4780_crtc.c features the following configuration register settings:

This seems to imply that the data enable, horizontal and vertical sync polarity are positive. The panel mode is unset, implying a generic TFT panel mode.

The driver appears to enable output FIFO overrun interrupts (OFUM) in the control register, resetting the controller if they occur during operation. Other drivers tend to enable overrun protection (OFUP) instead.

The driver enabled end-of-frame interrupts, sending vertical blanking events to the DRM infrastructure. End-of-frame conditions are activated by the DMA controller after frames have been transferred, and this is configured in the DMA descriptors.

The driver employs two 8-word DMA descriptors with the following format:

Field Description
Next Physical address of next frame descriptor
Source Physical address of source data to transfer
Frame Frame identifier (for debugging)
Command DMA command and transfer length (in words)
Offset OFFSIZE: Offset in words between lines
Page width PW: Number of words per line (16x16 block mode)
Command (smart LCD) CNUM: Command number (smart LCD mode)
Position (LCD) CPOS: Foreground position and properties
Foreground size DESSIZE: Foreground size and alpha properties

Note that the seventh word has two different interpretations depending on the CMD field (bit 29) of a transfer command.

In the driver, the next, source and frame fields are mostly comparable to those set by other drivers. However, the command is also initialised with a frame-enable flag.

The additional fields are initialised as follows:

Quite why these extra details need to be set up is not clear, but perhaps the OSD functionality must be enabled for the HDMI pipeline to work. Despite this, the OSD configure (OSDC) register is not apparently configured in the driver or elsewhere.

The 3.0.8 framebuffer driver (drivers/video/jz4780-fb/jz4780_fb.c) does configure the OSDC register with the following settings:

This driver only appears to configure the OSD control (OSDCTRL) register to enable the IPU clock on request.

Other interesting aspects of the 3.18 driver are the use of the RGB control (RGBC) and priority level threshold configure (PCFG) registers. The former is set up as follows:

The priority level threshold configuration register is set up as follows: