SMB (I2C)

Master mode operation...

Configuration

  1. Set SMBENB to 0.

  2. Wait for SMBENBST.SMBEN to become cleared.

  3. Set SMBCON.SPD to 0b01 for 100kbps to 0b10 for 400kbps.

  4. Configure SMB[SF][LH]CNT according to the speed and clock configuration.

  5. Configure SMBSDAHD.

  6. Configure buffer thresholds and interrupts (see below).

  7. Write the addressed device to SMBTAR.

  8. Set SMBTAR.MATP to 0 for 7-bit addressing or 1 for 10-bit addressing.

  9. Set SMBENB to 1.

  10. Wait for SMBENBST.SMBEN to become set.

For a master using 7-bit addressing, accessing a DDC device, the following would be done specifically:

  1. Set SMBCON: STPHLD = 0, SLVDIS = 1, REST = 1, SPD = 0b10 (perhaps), MD = 1

  2. Set SMBTAR: MATP = 0, SPECIAL = 0, SMBTAR = address

Buffers

Not explicitly described in the manual's configuration guidance, the following buffer control registers may be set:

SMBRXTL
Set the receive buffer threshold for a buffer full interrupt.
SMBTXTL
Set the transmission buffer threshold for a buffer full interrupt.

Interrupts

Not explicitly described in the manual's configuration guidance, the following interrupt configuration registers may be set:

SMBINTM
Mask interrupt conditions exposed by the SMBINTST register.

DMA Configuration

The following registers can apparently be configured to control DMA behaviour:

SMBDMACR
TDEN (bit 1) is transmit enable, RDEN (bit 0) is receive enable.
SMBDMATDLR
TDLR (bits 4..0) controls a buffer threshold at or below which more data is read via DMA for transmission.
SMBDMARDLR
RDLR (bits 4..0) controls a buffer threshold at or above which more received data is written via DMA.

Reading

  1. Set SMBDC.CMD to 1.

  2. Ensure that the reception buffer has data.

  3. Read SMBDC.DAT to obtain the data.

Presumably, reading from SMBDC is sufficient to update the reception buffer.

To read EDID data from a DDC device, it would presumably be possible in the simplest case to just write 0x100 to SMBDC repeatedly to reserve a number of buffer entries and to test for incoming data using either the SMBRXFLR register (indicating the number of valid data entries) or employing SMBST.RFNE (buffer not empty).

To batch reads, the buffer full threshold could be set to a reasonable amount, and upon detecting the SMBINTST.RXFL (buffer full) condition, multiple reads could then be performed.

Reading Using DMA

The DMA mechanism would be set up as follows:

  1. DRTn (DMA request type for channel n) would be set to 37 (SMB0 receive full), 39 (SMB1), 41 (SMB2), 43 (SMB3), or 45 (SMB4).

Writing

  1. Ensure that the transmission buffer has free space.

  2. Set SMBDC.CMD to 0, SMBDC.DAT as the data to be written.

Presumably, writing to SMBDC is sufficient to update the transmission buffer.

Registers

SMBENB

Enable/disable.

Field Bits Description/Setting
... 31..1 ...
SMBENB 0 1 to enable SMB, 0 to disable

Disabling during transfers completes the transfer (presumably the current contents of the transfer buffer) and issues a stop condition. Disabling during reception obtains the current byte but sends no acknowledgement condition.

SMBCON

Configuration.

Field Bits Description/Setting
... 31..8 ...
STPHLD 7 1 to prevent STP being automatically sent
SLVDIS 6 1 to prevent slave mode after reset
REST 5 1 to permit restart conditions
MATP 4 Corresponds to SMBTAR.MATP
SATP 3 1 to respond to 10-bit, not 7-bit addresses
SPD 2..1 0b10 for 400kbps, 0b01 for 100kbps
MD 0 1 to enable master

It might be useful to always assert SLVDIS to avoid state issues in the peripheral. It might also be useful to assert REST for robustness. For master mode, MD needs to be set.

SMBTAR

Target address.

Field Bits Description/Setting
... 31..13 ...
MATP 12 1 for 10-bit, 0 for 7-bit, addressing
SPECIAL 11 1 for special call, 0 for normal addressing
GC_OR_START 10 1 for start byte, 0 for general call
SMBTAR 9..0 Target address

SMBDC

Data transmission and reception.

Field Bits Description/Setting
... 31..9 ...
CMD 8 1 to read, 0 to write
DAT 7..0 Data for transmission