HDMI

Some notes about the HDMI driver, found in the specific 3.18 kernel at drivers/gpu/drm/jz4780. The newer generic driver is found in more recent kernels at drivers/gpu/drm/bridge/synopsys/dw-hdmi.c. Meanwhile, the older HDMI driver functionality can be found in the specific 3.0.8 kernel at drivers/video/jz4780-hdmi.

State

In dwc_hdmi.h, struct dwc_hdmi retains state for various things:

• Device type details, used to distinguish between different configurations of the common functionality
• Device tree node reference
• DRM connectors, encoders and devices
• HDMI data, featuring input and output formats, HDCP status, video mode details
• Audio device reference
• Clock references
• DDC device reference
• Display mode information
• EDID information
• Peripheral register details
• Pixel and sample clock rates

Initialisation

The probe operation in dwc_hdmi.c obtains device details from the device tree:

• Device type details: "dwc-hdmi" should yield a type of DWC_HDMI
• DDC device reference (this is I2C4 employing port F in the CI20)
• Interrupt details from the "interrupt-parent" and "interrupts" properties
• Peripheral register memory from the "reg" property
• Register stepping details from the "reg-shift" property
• HDMI/SFR and AHB clock details using the "clocks" and "clock-names" properties
• HDMI clock frequency from the "clock-frequency" property

Some other operations occur:

• HDMI block interrupts are reset
• HDMI block clocks are configured using the pixel and sample rates
• HDMI block interrupts are enabled
• Driver state information is populated

The 3.0.8 driver sets the following parameters in hdmi_init, with parameter documentation in core/audioParams.h and core/videoParams.h:

Clock Configuration

The 3.18 device tree in arch/mips/boot/dts/jz4780.dtsi has a node setting the clock frequency to 27MHz. In the 3.0.8 kernel driver, the probe mechanism in jz4780_hdmi.c sets the same frequency.

Power Configuration

The 3.18 device tree in arch/mips/boot/dts/ci20.dts configures an active-high, always-on fixed regulator on GPIO A25.

The 3.0.8 kernel obtains a reference to the vhdmi regulator but does not seem to manipulate it. This regulator is defined in various board definitions in arch/mips/xburst/soc-4780/board.

Power control is actually performed by a separate regulator IC whose 3.0.8 and 3.18 drivers are found in drivers/regulator/act8600-regulator.c.

The power supply to the PHY is set in the dwc_hdmi_phy_enable_power function which sets the PDZ flag in the HDMI_PHY_CONF0 register.

Register Access

The 3.0.8 driver defines register access primitives in bsp/access.c that employ 16-bit addresses (relative to the peripheral base address) and 8-bit values.

The 3.18 kernel maintains this style of access with the hdmi_readb and hdmi_writeb functions.

More recent kernels maintain this style of access, too. See drivers/gpu/drm/bridge/synopsys/dw-hdmi.c.

Registers

From dwc_hdmi_regs.h in 3.18. More recent kernels have a more comprehensive set of definitions in drivers/gpu/drm/bridge/synopsys/dw-hdmi.h.

Identification Registers

PHY Registers

HDMI_PHY_I2CM_OPERATION_ADDR

HDMI_PHY_CONF0

Interrupt Registers

HDMI_IH_MUTE

Presumably, the ALL_INTERRUPT flag prevents specific interrupt conditions from occurring if set, even if those are enabled individually.

PHY Interrupt Registers

HDMI_IH_PHY_STAT0

HDMI_IH_I2CMPHY_STAT0

HDMI_IH_MUTE_PHY_STAT0

HDMI_IH_MUTE_I2CMPHY_STAT0

Overflow Interrupt Registers

FC stands for Frame Composer.

I2C Signalling

There is a connection employing I2C to the PHY that involves the hdmi_phy_i2c_write function. This uses the HDMI peripheral's own I2C functionality, not the JZ4780 I2C peripherals. (Note that this peripheral can also be used to query the DDC for EDID information.)

The hdmi_phy_wait_i2c_done function is used after each write operation to test whether the transfer was successful by testing the lower two bits of HDMI_IH_I2CMPHY_STAT0 every millisecond until one of the bits is set. The overall timeout in the __hdmi_phy_i2c_write function is one second.

The __hdmi_phy_i2c_write function does the following:

1. Writes 0xFF to HDMI_IH_I2CMPHY_STAT0 to clear all I2C PHY interrupt conditions.
2. Writes a register address to HDMI_PHY_I2CM_ADDRESS_ADDR.
3. Writes output data to HDMI_PHY_I2CM_DATAO_0_ADDR and HDMI_PHY_I2CM_DATAO_1_ADDR.
4. Writes an operation code to HDMI_PHY_I2CM_OPERATION_ADDR.
5. Waits for completion.

Audio Sampling

The pixel clock appears to be converted to two quantities: n and cts.

According to the driver, the JZ4780 uses "automatic CTS/N generation" and clears the HDMI_AUD_CTS3_CTS_MANUAL bit of HDMI_AUD_CTS3. According to the newer driver, CTS only needs setting for other SoCs if "internal AHB audio" is used (discovered by testing the HDMI_CONFIG3_AHBAUDDMA bit of HDMI_CONFIG3_ID).

The older driver seems to test pixel clock and sample rate combinations, returning various predefined results, whereas the newer driver calculates it as follows:

cts = (pixel_clock * n) / (128 * sample_rate)

For n, both drivers appear to test pixel clock and sample rate combinations, returning an appropriate value.

According to dwc_hdmi_regs.h, the hardware appears to provide three byte-sized registers together supporting a 20-bit value for n:

The different portions of n are presented to these registers, and a field is cleared in the HDMI_AUD_CTS3 register to assert HDMI_AUD_CTS3_N_SHIFT_1, which perhaps causes n to be shifted by 1.

Enabling Output

In the 3.18 driver, the HDMI output is enabled when one of the following occurs:

• The HDMI cable is plugged in (the HDMI_IH_PHY_STAT0 register has the HPD flag set, and the HDMI_PHY_POL0 register has the HPD flag set to indicate a plug-in event).
• A DPMS operation indicates a powering up condition (dwc_hdmi_encoder_dpms).
• A commit operation occurs (dwc_hdmi_encoder_commit).

These cause the dwc_hdmi_poweron function to be called which in turn calls dwc_hdmi_setup. This performs a number of operations as described below.

1. Overflow interrupts are disabled (hdmi_disable_overflow_interrupts).
2. Video mode configuration is performed, employing drm_match_cea_mode to match a CEA-861 mode, returning a VIC (video identifier), adjusting various parameters. Without a CEA mode, DVI-compatible output is selected.
3. The input and output video encoding formats are set to RGB.
4. Picture configuration is performed (hdmi_av_composer).
5. PHY initialisation is performed (dwc_hdmi_phy_init). This involves the hdmi_phy_configure function and ultimately the enabling of power to the peripheral (dwc_hdmi_phy_enable_power).
6. dwc_hdmi_enable_video_path
7. hdmi_clk_regenerator_update_pixel_clock
8. hdmi_enable_audio_clk
9. hdmi_config_AVI
10. hdmi_video_packetize
11. hdmi_video_csc
12. hdmi_video_sample
13. hdmi_tx_hdcp_config
14. dwc_hdmi_clear_overflow
15. If connected and not in DVI mode, hdmi_enable_overflow_interrupts is invoked.

PHY Configuration

I2C operations involve setting the device to HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 and performing configuration operations using I2C writes. The following registers are involved:

CPCE_CTRL

Address 0x06 (CPCE_CTRL) is written with a value that appears to set various bits according to the selected colour depth/resolution:

This value is combined with a value that appears to be connected to the pixel clock frequency.

For a colour depth of 8, the final value is given as 0x00a0 in the 3.18 and more recent drivers without explanation.

GMPCTRL

Address 0x15 (GMPCTRL) is written with a value that apparently corresponds to the pixel clock frequency range:

For a colour depth of 8, the final value is given as 0x000a in the 3.18 and more recent drivers without explanation.

CURRCTRL

Address 0x10 (CURRCTRL) appears to use values related to colour resolution and frequency range in various combinations.