VGA Output Example (Dual-Channel DMA Transfers)

This example demonstrates the generation of an analogue VGA signal from a PIC32 microcontroller using general output pins. It follows on from the work done in the VGAPIC32 project. The result is not entirely satisfactory:

It might be possible to introduce some kind of delay and even out the pixel widths, but this has not been investigated with hardware. However, unlike the vga-pmp example, there is no accompanying signal to potentially orchestrate the staging of individual pixels at a slightly delayed rate. Potentially, the peripheral clock signal might be generated and processed to make such a signal.

Unlike the vga example, this example employs two DMA channels for pixel data which are interleaved to investigate a potential remedy for the wide pixel effect. Unfortunately, despite each channel contributing every other word (or group of four pixels), the effect persists. However, the picture is perhaps more stable than in the vga example.

One significant problem with this example is that scrolling causes the DMA channels to become ordered incorrectly. This does not affect the vga-timer example which also employs two DMA channels.

Hardware Details

The pin usage of this solution is documented below.

PIC32MX270F256B-50I/SP Pin Assignments

MCLR#          1  \/  28
HSYNC/OC1/RA0  2      27
VSYNC/OC2/RA1  3      26 RB15/U1TX
       D0/RB0  4      25 RB14
       D1/RB1  5      24 RB13/U1RX
       D2/RB2  6      23
       D3/RB3  7      22 RB11/PGEC2
               8      21 RB10/PGEC3
          RA2  9      20
          RA3 10      19
       D4/RB4 11      18 RB9
              12      17 RB8
              13      16 RB7/D7
       D5/RB5 14      15

Note that RB6 is not available on pin 15 on this device (it is needed for VBUS unlike the MX170 variant).

UART Connections

UART1 is exposed by the RB13 and RB15 pins.

Data Signal Routing

For one bit of intensity, two bits per colour channel:

D7 -> 2200R -> I

I -> diode -> R
I -> diode -> G
I -> diode -> B

D6 (not connected)

D5 -> 470R -> R
D4 -> 1000R -> R
D3 -> 470R -> G
D2 -> 1000R -> G
D1 -> 470R -> B
D0 -> 1000R -> B

HSYNC -> HS
VSYNC -> VS